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An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture.
There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. These two global and 16 individual architecture bits define all possible configurations a GAL16V8. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits.
These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable OE usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively.
These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins pins 15 and 16 will not have the feedback option as these pins are always configured as dedicated combinatorial output.
GAL16V8D-25LP Lattice, GAL16V8D-25LP Datasheet - Page 3